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| About the authors |
Zainalabedin Navabi, Ph.D., navabi@ece.neu.edu, is adjunct professor of electrical and computer engineering at Northeastern University and the author of both editions of VDHL: Analysis and Modeling of Digital Systems, published by McGraw-Hill. Since 1981, Dr. Navabi has worked in the design, definition and implementation of hardware description languages and the synthesis and testing of digital systems. He has developed and supervised the development of many HDL-related software packages and tools, and has directed projects in VLSI design, test synthesis, simulation, synthesis, and other aspects of digital system automation. He has served as a consultant for several EDA companies developing HDL based tools and environments. Dr. Navabi is a member of ACM, IEEE, IEEE computer society, and an active participant in IEEE DASC committee that sets standards related to hardware description languages |
| Table of contents |
Preface Introduction Acknowledgments Chapter 1: Digital System Design Automation with VHDL Chapter 2: RTL with VHDL Chapter 3: VHDL Constructs for Structure and Hierarchy Descriptions Chapter 4: Concurrent Constructs for RT Level Descriptions Chapter 5: Sequential Constructs for RT Level Descriptions Chapter 6: VHDL Language Utilities and Packages Chapter 7: VHDL Signal Model Chapter 8: Hardware Cores and Models Chapter 9: Core Design and Testability Chapter 10: Design, Test and Application of a Processor Core APPENDIX A: VHDL KEYWORDS APPENDIX B: VHDL LANGUAGE GRAMMAR APPENDIX C: VHDL STANDARD PACKAGES APPENDIX D: STD_LOGIC_1164 Package APPENDIX E: STD_LOGIC_TEXTIO Package APPENDIX F: STD_LOGIC_ARITH Package APPENDIX G: STD_LOGIC_SIGNED APPENDIX H: STD_LOGIC_UNSIGNED APPENDIX I: math_real Package INDEX |
